This invention relates to improvements in thin film transistors .(TFTs), and more particularly to improvements in TFT devices with organic semiconductors.
(The following section contains background material that, unless specifically stated otherwise, may or may not be prior art).
Over the last decade, IC technologies have been proposed that use organic semiconductor thin film transistors (TFTs). The chief attractions of such circuits stem from the anticipated ease of processing and compatibility with flexible substrates. These advantages are expected to translate into a low-cost IC technology suitable for applications such as smart cards, electronic tags, and displays.
TFT devices are described in F. Gamier et al., Science, Vol. 265, pp. 1684-1686; H. Koezuka et al., Applied Physics Letters, Vol. 62 (15), pp. 1794-1796; H. Fuchigami et al., Applied Physics Letters, Vol. 63 (10), pp. 1372-1374; G. Horowitz et al., J. Applied Physics, Vol. 70(1), pp. 469475; and G. Horowitz et al., Synthetic Metals, Vol. 42-43, pp. 1127-1130. The devices described in these references are based on polymers or oligomers as the active materials, in contrast with the amorphous silicon and polysilicon TFT structures that were developed earlier. The devices are typically field effect transistors (FETs). Polymer active devices have significant advantages over semiconductor TFTs in terms of simplicity of processing and resultant low cost. They are also compatible with polymer substrates used widely for interconnect substrates. Polymer TFTs are potentially flexible, and polymer TFT ICs can be formed directly on flexible printed circuit boards. They also have compatible coefficients of thermal expansion so that solder bonds, conductive expoxy bonds, and other interconnections experience less strain than with semiconductor IC/polymer interconnect substrate combinations. While metal-insulator-semiconductor (MIS) FET devices are most likely to find widespread commercial applications, TFT devices that utilize both p-type and n-type organic active materials are also known. See e.g., U.S. Pat. No. 5,315,129. S. Miyauchi et al., Synthetic Metals, 41-43 (1991), pp. 1155-1158, disclose a junction FET that comprises a layer of p-type polythiophene on n-type silicon.
Recent advances in polymer based TFT devices are described in U.S. Pat. No. 5,596,208, issued May 10, 1996, U.S. Pat. No. 5,625,199, issued Apr. 29, 1997, and U.S. Pat. No. 5,574,291, issued Nov. 12, 1996. With the development of both n-type and p-type active polymer materials, as described in these patents, complementary ICs can be readily implemented, as detailed particularly in U.S. Pat. No. 5,625,199.
With the basic organic TFT technology now well established, refinements in the device structures and processing can be expected. Electronic systems that combine plastic substrates and printing techniques with new classes of organic, hybrid organic-inorganic, or solution-derived inorganic semiconductors represent important emerging technologies. See for example: C. A. Mirkin, J. A. Rogers, MRS Bull. 26, 530 (2001); Z. Bao, J. A. Rogers, H. E. Katz, J. Mater. Chem. 9, 1895 (1999); C. R. Kagan, D. B. Mitzi, C. D. Dimitrakopoulos, Science 286,945 (1999); B. A. Ridley, B. Nivi, J. M. Jacobson, Science 286,746 (1999); R. F. Service, Science 287,415 (2000).
Plastic circuits have attractive characteristics that are difficult to achieve with materials and methods used for conventional electronics: they are mechanically flexible, durable and lightweight, and they can be printed over large areas. Recent advances in TFT fabrication methods use lamination techniques wherein part of the transistor structure is formed on one substrate and the remaining transistor elements are formed on another substrate. The two substrates are then joined together to complete the transistor. They also have the potential to be ultralow in cost partly because they are compatible with continuous, high speed reel-to-reel fabrication techniques. See H. Sirringhaus et al, Science 290, 2123 (2000); J. A. Rogers, Z. Bao, A. Makhija, Adv. Mater. 11, 741 (1999); C. J. Drury, C. M. J. Mutsaers, C. M. Hart, M. Matters, D. M. de Leeuw, Appl.; and U.S. Pat. No. 6,197,663, issues Mar. 6, 2001. These references are incorporated by reference herein for processing details. In this method, the flexible substrates that are to be joined together are formed on a continuous flexible tape, and the tapes reeled on a rotating drum. Joining the two tapes together simply involves unreeling them from drums, and spooling them together in mating relationship. Pressure or simple contact, or a curing influence such as heat or UV radiation, bonds the tapes together to form a single tape. The single tape is cut as desired to form individual TFT transistors, or groups of transistors. The tapes may even carry simple transistor circuits.
As a result, plastic circuits will form the foundations for future devicesxe2x80x94electronic paper, wearable sensors, low cost smart cards and RF identification tags, flexible arrays of plastic microphones, etc.xe2x80x94that will complement the types of systems that established electronics supports well (e.g. microprocessors, high density RAM).
Recent results demonstrate several promising combinations of materials and patterning techniques for small (several transistors) to medium (several hundred transistors) scale plastic circuits. These systems, however, are fabricated in a general approach that was borrowed from conventional silicon microelectronics: they are built by depositing and patterning one material layer after another on a single substrate. Designing sets of chemically compatible solution-processable materials that can be reliably deposited on top of plastic substrates and on top of one another in this layer-by-layer approach is challenging. Requirements that follow from this fabrication strategy often lead to transistor and circuit geometries that are not optimized for electrical performance. Similar concerns make it difficult to incorporate designs that improve the mechanical flexibility of the circuits. Efficient and general means for encapsulating the devices are also lacking; their environmental stability is, as a result, typically poor or unknown.
The lamination approach has proven reliable and cost effective. However, improvements in the lamination technique continue to be sought in order to further reduce cost and increase reliability.
The invention described in more detail below is a method for using xe2x80x98softxe2x80x99, conformable electrical contacts and lamination procedures to fabricate printed plastic circuits. In this approach, different parts of a circuit are fabricated on different substrates; at least one of these incorporates high resolution, conformable electrical contacts. Bonding the substrates together forms embedded, high performance circuits. According to the invention, the substrates are bonded together using solid adhesive polymer layers of low elastic modulus. These materials form a reliable bond under conditions that allow fast and controllable adhesion, suitable for reel-to-reel assembly mentioned above. The bond conditions include room temperature to 150xc2x0 C., and zero to 50 psi pressure.
This approach has many practical advantages, including the ability (i) to separate many of the patterning and deposition steps, (ii) to enable transistors with geometries that are conducive to high performance, (iii) to produce embedded circuits that are highly resistant to fracture during bending, and (iii) to form completely encapsulated devices.
In the preferred embodiment a first flexible polymer substrate is coated with the low modulus solid adhesive polymer layer. The TFT elements are formed on the solid adhesive polymer layer, and the first flexible polymer layer is laminated to a second flexible polymer layer using the solid adhesive polymer layer to bond the first and second substrates together. Reference to TFT elements includes the electrical contacts for source, drain or gate, or printed interconnections for those transistor elements, and the semiconductor layer of the TFT. The solid adhesive polymer layer functions both as a substrate or support for the TFT elements, and an adhesive for the laminating the plies together. In a second embodiment, one or more TFT elements are formed on a solid adhesive polymer layer on the first flexible substrate, and one or more TFT elements are formed on a second solid adhesive polymer layer on the second flexible substrate.
In a third embodiment, all the TFT elements are formed on a solid adhesive polymer layer on a first flexible polymer substrate which is laminated to a second flexible polymer substrate.
In a fourth embodiment, all the TFT elements are formed on a first flexible polymer substrate which is laminated to a second flexible polymer substrate by means of a solid adhesive polymer layer on the second polymer substrate.
In each of these embodiments the flexible polymer may itself function as the solid adhesive polymer layer. In the preferred case, the solid adhesive polymer layer is an elastomer.
In addition to the two plies implicit in the embodiments just described, additional plies may be used to implement interconnection levels. A multilevel structure that can be fabricated according to the invention is described in U. S. patent application Ser. No. 10/024,831 filed Dec. 08, 2001.